The present invention relates to a semiconductor memory device for storing data by using a ferroelectric capacitor in a part of a memory cell and to an electronic apparatus mounting the semiconductor memory device.
As an example of a conventional semiconductor memory device having a memory cell composed of a ferroelectric capacitor and a transistor, there has been known one having a structure as shown in FIG. 10. As shown in FIG. 10, the memory cell of the semiconductor memory device has a ferroelectric capacitor 10 and a transistor 20. The ferroelectric capacitor 10 has a ferroelectric film composed of SrBi2Ta2O9 with a thickness of 200 nm. The ferroelectric capacitor 10 has a first electrode 11 connected to the source 21 of the transistor 20 and a second electrode 12 connected to a cell plate line 31. The transistor 20 has a drain 22 connected to a bit line 32 and a gate electrode 23 connected to a word line 33.
In FIG. 10, 34 denotes a word line driver (WLD) for selecting the word line 33, 35 denotes a cell plate driver (CPD) for driving the cell plate line 31, 36 denotes a sense amplifier (SA) for differentially amplifying a voltage on the bit line 32, 37 denotes a reference voltage generator (RVG) necessary for the differential amplifying operation of the sense amplifier 46, and 38 denotes a bit line capacitance which is the capacitance of the bit line 32 represented by a circuit symbol.
In the following description, the one of polarizations induced upon the application of a voltage between the first and second electrodes 11 and 12 of the ferroelectric capacitor 10 which is observed in the ferroelectric capacitor 10 even after the applied voltage is removed will be termed a remanent polarization.
FIG. 11 shows the hysteresis loop y of the ferroelectric capacitor 10 when, after sets of data “1” and data “0” are written in the memory cell shown in FIG. 10, the operation of reading these data sets is performed. In the case of writing data in the memory cell shown in FIG. 10, if the charge accumulated in the first electrode 11 of the ferroelectric capacitor 10 has a negative polarity after the writing of the data, it is determined that the data “0” has been written by associating the displacement of the remanent polarization in the ferroelectric capacitor 10 with the point p in FIG. 11 and, if the charge accumulated in the first electrode 11 of the ferroelectric capacitor 10 has a positive polarity after the writing of the data, it is determined that the data “1” has been written by associating the displacement of the remanent polarization in the ferroelectric capacitor 10 with the point q in FIG. 11.
-Operation of Writing Data “1”-
FIG. 12A shows respective timings for potentials on the individual signal lines for writing the data “1” in the memory cell. Specifically, the potential on the word line 33 is raised from a L level to a H level at the time T1 so that the transistor 20 is turned ON. Then, at the time T2, the potential on the cell plate line 31 is raised to the H level, while the setting of the potential on the bit line 32 is kept at the L level, so that a potential difference (H−L) is produced in the ferroelectric capacitor 10 to orient the polarization in an upward direction and the data “1” is thereby written in the bit line 32. Even if the data “0” is written in the state prior to the writing of the data “1”, i.e., if the polarization is facing downward, the (H−L) potential difference should have a value sufficiently exceeding a coercive voltage Vc necessary for polarization inversion in the ferroelectric capacitor 10 to ensure the rewriting of the data “0” to the data “1”. If the ferroelectric film of the ferroelectric capacitor 10 is, e.g., a SrBi2Ta2O9 film having a thickness of 200 nm, the coercive voltage of the ferroelectric capacitor 10 is about 1 V so that the foregoing requirement is fully satisfied if the potential difference (H−L) is 5 V.
-Operation of Writing Data “0”-
FIG. 12B shows respective timings for potentials on the individual signal lines for writing the data “0” in a memory cell. Specifically, the potential on the word line 33 is raised from a L level at, e.g., 0 V to a H level at, e.g., 5 V at the time T1 so that the transistor 20 is turned ON. Then, at the time T2, the potential on the cell plate line 31 is raised to the H level and the potential on the bit line 32 is also raised to the H level (data “0”). Thereafter, the potential on the cell plate line 31 is lowered to the L level at the time T3 so that a potential difference (H−L) is produced in the ferroelectric capacitor 10 to orient the polarization in the downward direction and the data “0” is thereby written in the bit line 32. Even if the data “1” is written in the state prior to the writing of the data “0”, i.e., if the polarization is in the upward direction, the foregoing sequence of operations ensures the rewriting of the data “1” to the data “0”.
-Operation of Reading Data “1”-
FIG. 13A shows respective timings for potentials on the individual signal lines in a read operation to the memory cell in which the data “1” has been written.
In reading the data, the potential on the bit line 32 is preliminarily lowered to the L level and then, at the time t1, the potential on the word line 33 is raised to the H level so that the transistor 20 is turned ON.
Then, at the time t2, the potential on the cell plate line 31 is raised to the H level. At this time, the bit line 32 is in the state connected to the sense amplifier 36 and retains the bit line capacitance 38. It follows therefore that a series capacitive coupling is formed by the cell plate line 31, the capacitance of the ferroelectric capacitor 10, the bit line capacitance 38, and the substrate. Consequently, the majority of the voltage applied to the cell plate line 31 is applied to the ferroelectric capacitor 10. The voltage is sufficiently higher than the coercive voltage Vc but the remanent polarization is upwardly deviated when the data “1” is written so that the bit line capacitance 38 is charged, while the deviated polarization undergoes a relatively small change. As a result, the potential on the bit line 32 at the time t3 is as low as 2 V at the maximum.
If the sense amplifier 36 is activated at the time t3 by setting, to 2.5 V, the signal inputted from the reference voltage generator 37 to the sense amplifier 36, the potential on the bit line 32 is lowered to the L level and it is determined that the potential on the bit line 32 is at the L level, i.e., that data “1” has been written.
At the time of reading the data “1”, the remanent polarization in the ferroelectric capacitor 10 is not inverted so that the data in the memory cell is restored to the state before the read operation by lowering the potential on the cell plate line 31 to the L level at the time t4, lowering the potential on the bit line 32 to the L level at the time t5, and lowering the potential on the word line 33 to the L level at the time t6.
-Operation of Reading Data “0”-
FIG. 13B shows respective timings for potentials on the individual signal lines in a read operation to the memory cell in which the data “0” has been written.
In reading the data, the potential on the bit line 32 is preliminarily lowered to the L level and then, at the time t1, the potential on the word line 33 is raised to the H level so that the transistor 20 is turned ON.
Then, at the time t2, the potential on the cell plate line 31 is raised to the H level. At this time, the voltage applied to the cell plate line 31 is divided into a voltage applied to the ferroelectric capacitor 10 and a voltage applied to the bit line capacitance 38.
However, since the magnitude of the bit line capacitance 38 is about 5 to 10 times larger than the capacitance of the ferroelectric capacitor 10, the majority of the voltage applied to the cell plate line 31 is applied to the ferroelectric capacitor 10. Since the voltage is sufficiently higher than the coercive voltage Vc, the bit line capacitance 38 is charged, while the orientation of the polarization is inverted from the downward direction to the upward direction and the deviated polarization undergoes a relatively large change. This state will be understood from the movement of a point of intersection of the hysteresis loop y of the ferroelectric capacitor 10 and the read load line r for the data “0”. At the time t3, the potential on the bit line 32 has been raised to about 3 V by the charging of the bit line capacitance 38.
In this state, if the sense amplifier 36 is activated at the time t3 by setting, to 2.5 V, the signal inputted from the reference voltage generator 37 to the sense amplifier 36, the potential on the bit line 32 is amplified to the H level and it is determined that the potential on the bit line 32 is at the H level, i.e., that data “0” has been written.
If the voltage on the bit line 32 is latched here, the data reading operation is completed. However, the remanent polarization in the ferroelectric capacitor 10 has been inverted from the downward direction to the upward direction, as described above. To restore the inverted state to the original state, a rewrite operation is performed. Specifically, the potential on the cell plate line 31 is lowered to the L level at the time t4 in FIG. 13B, while the setting of the potential on the bit line 32 is kept at the H level, whereby a potential difference (H−L) is produced between the bit line 32 and the cell plate line 31. By thus orienting the remanent polarization in the ferroelectric capacitor 10 to the downward direction again, the data “0” is written again. Thereafter, the potential on the bit line 32 is lowered to the L level at the time t5, while the potential on the word line 33 is lowered from the H level to the L level at the time t6.
By the foregoing operation, the memory cell holding the data “0” is restored to the state prior to the read operation.
Thus, in the conventional ferroelectric memory device, polarization inversion is necessary to rewrite the data held in the ferroelectric capacitor 10. Moreover, at least the operation of reading the data “0” from the memory cell cannot be performed unless the polarization in the ferroelectric capacitor 10 is inverted such that the bit line capacitance 38 having a magnitude 5 to 10 times larger than the capacitance of the ferroelectric capacitor 10 is charged. In short, the inversion of the remanent polarization is necessary in the data write operation and the data read operation.
However, since the phenomenon of polarization fatigue is observed in a ferroelectric film, the ferromagnetic film is degraded in the ability to exhibit distinct polarization if the operation of inverting the polarization is repeated.
If the writing or reading of data is repeatedly performed in the conventional ferroelectric memory device, the problem is encountered that the operating lifetime of the ferroelectric memory device is limited by the polarization fatigue of the ferroelectric film.
The polarization fatigue of the ferroelectric material can be recognized in, e.g., FIG. 14 in which the difference (hereinafter represented by 2Pr) between the magnitude of the remanent polarization when the data “0” is written and the magnitude of the remanent polarization when the data “1” is written gradually decreases with the repetitive application of a positive or negative voltage pulse. If the number of polarization inversions induced by the application of the positive or negative voltage pulse approaches 1010 times, the value 2Pr rapidly decreases.
The degree of the polarization fatigue in the ferroelectric film is dependent on the voltage of the voltage pulse. If it is assumed that the number of polarization inversions till the value 2Pr of a ferroelectric capacitor composed of SrBi2Ta2O9 with a thickness of 200 nm decreases to 50% of the initial value is the rewritable number of times, the voltage dependence of the rewritable number of times as shown in FIG. 15 is obtained. That is, if the rewrite voltage is lowered, the polarization fatigue is suppressed and the rewritable number of times is increased exponentially.
As a method for suppressing the polarization fatigue of the ferroelectric film, e.g., the lowering of the rewrite voltage to a sufficiently low value can be considered. Specifically, if the rewrite voltage is lowered to 1.5 V or less in the case shown in FIG. 15, the rewritable number of times of 1015 or more is achievable.
In the ferroelectric capacitor, however, there is normally a voltage for performing the operation of writing data “1” or data “0” in the memory cell. If the write voltage is set to a low value which allows 1015 times or more rewrite operations, the displacement of the remanent polarization (in this case, the value 2Pr serves as an index) is rapidly reduced, which causes the following problem.
As shown in FIG. 16, the displacement of the remanent polarization depends on a data rewrite voltage. As shown in FIG. 17, the displacement of the remanent polarization depends on a data retention time so that it decreases with the lapse of the data retention time.
Therefore, the time during which data can be retained, i.e., the lifetime of the ferroelectric capacitor is determined based on the initial displacement of the remanent polarization. As can be seen from FIG. 17, e.g., a write voltage (which is 5 V in FIG. 16) which saturates the remanent polarization substantially completely is necessary for the initial displacement of the remanent polarization to provide a sufficiently long data retention lifetime (longer than 105 hours).
To render the ferroelectric capacitor rewritable 1015 or more times, it is necessary to adjust the write voltage to 1.5 V or less. However, the initial displacement of the remanent polarization obtained with such a low write voltage is 10 μC/cm2 at the maximum and the data retention lifetime expected therefrom is several hundred hours at the maximum.
Thus, in the conventional semiconductor memory device, it has been difficult to increase the rewritable number of times of the ferroelectric capacitor by using a lower write voltage and provide a sufficiently long data retention lifetime at the same time.